Program 2016

Time Description
9:00-9:10 Opening
John Wawrzynek [Slides (pdf)]
9:10-9:30

Automated Space/Time Scaling of Streaming Task Graph
Hossein Omidian and Guy Lemieux [Presentation Slides (pdf)]
9:30-9:50

An Area-Efficient FPGA Overlay Architecture using Time-multiplexed DSP Block based Functional Units
Xiangwei Li, Abhishek Jain, Douglas Maskell and Suhaib Fahmy [Presentation Slides (pdf)]
9:50-10:10

High Level Synthesis with a Dataflow Architectural Template
Shaoyi Cheng and John Wawrzynek [Presentation Slides (pdf)]
10:10-10:20

Reliability-Aware Overlay Architectures for FPGAs: Features and Design
Mihalis Psarakis [Presentation Slides (pdf)]
10:20-10:30

GRVI Phalanx: A Massively Parallel RISC-V FPGA Accelerator Accelerator
Jan Gray [Presentation Slides (pdf)]
10:30-10:50 break
10:50-11:10

Soft GPGPUs for Embedded FPGAs: An Architectural Evaluation
Kevin Andryc, Tedy Thomas and Russell Tessier [Presentation Slides (pdf)]
11:10-11:30

A Soft Processor Overlay with Tightly-coupled FPGA Accelerator
Ho-Cheung Ng, Cheng Liu and Hayden Kwok-Hay So [Presentation Slides (pdf)]
11:30-11:50

Enabling Effective FPGA Debug using Overlays: Opportunities and Challenges
Fatemeh Eslami, Eddie Hung and Steven Wilton [Presentation Slides (pdf)]
11:50-12:00

A Dynamic Overlay Supporting Just-In-Time Assembly to Construct Customized Hardware Accelerators
Zeyad Aklah, Sen Ma and David Andrews [Presentation Slides (pdf)]
12:15-13:15 Panel discussion:
"I need that last MHz of performance, take that overlay away!"
  • Guy Lemieux, UBC, Canada [Slides (pdf)]
  • Jan Gray, Gray Research LLC [Slides (pdf)]
  • Hayden So, University of Hong Kong, Hong Kong [Slides (pdf)]
  • Steve Trimberger, Xilinx [Slides (pdf)]
  • Peter Yiannacouras, Altera [Slides (pdf)]
13:15 Closing