| 9:00-9:10 |
John Wawrzynek, Welcome and Opening Remarks |
| 9:10-9:30 |
Hayden So, "The State of FPGA Overlays"
|
| 9:30-10:30 |
Session 1 |
|
| 9:30-9:45 |
Jan Gray, GRVI Phalanx On Xilinx Virtex UltraScale+: A 1,680-core, 26 MB RISC-V Parallel Processor Overlay
|
| 9:45-10:00 |
Amit Kulkarni, Dirk Stroobandt, Andre Werner, Florian Fricke and Michael Huebner, Pixie: A heterogeneous Virtual Coarse-Grained Reconfigurable Array for high performance image processing applications
|
| 10:00-10:15 |
Abhishek Jain, Douglas L. Maskell and Suhaib A. Fahmy, Resource-Aware Just-in-Time OpenCL Compiler for Coarse-Grained FPGA Overlays
|
| 10:15-10:30 |
Joint Panel with Authors |
|
| 10:30-11:00 |
break |
| 11:00-12:00 |
Session 2 |
|
| 11:00-11:15 |
David Wilson and Greg Stitt, A Scalable, Low-Overhead Finite-State Machine Overlay for Rapid FPGA Application Development
|
| 11:15-11:30 |
Siddhartha and Nachiket Kapre, Out-of-order dataflow scheduling for FPGA Overlays
|
| 11:30-11:45 |
Guy Lemieux, Joe Edwards, Joel Vandergriendt, Aaron Severance, Abdullah Raouf, Tom Watzka, Satwant Singh and Guy Lemieux, TinBiNN: Tiny Binarized Neural Network Overlay in Less Than 5,000 4-LUTs
|
| 11:45-12:00 |
Joint Panel with Authors |
|
| 12:00 |
Closing |
